This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-352265, filed Nov. 20, 2000; and No. 2001-341392, filed Nov. 7, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a ferroelectric capacitor, particularly, to a semiconductor device having a highly integrated ferroelectric memory cell and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a ferroelectric memory cell is being developed as a non-volatile semiconductor memory device having a low power consumption and a high reliability. For example, a conventional ferroelectric memory device using a ferroelectric capacitor comprising a PZT (PbZr1xe2x88x92xTiOx) film is constructed as shown in FIG. 1.
As shown in the drawing, diffusion layers 101 to 103 are formed in a semiconductor substrate 100, and gates 104 to 107 are formed on the semiconductor substrate 100 adjacent to these diffusion layers 101 to 103. A plug 108 for connecting the diffusion layer 101 to a lower electrode 111 of a ferroelectric capacitor is formed on the diffusion layer 101. Likewise, a plug 109 for connecting the diffusion layer 102 to a wiring 121 is formed on the diffusion layer 102. Further, a plug 110 for connecting the diffusion layer 103 to a lower electrode 117 of a ferroelectric capacitor is formed on the diffusion layer 103.
The lower electrode 111 common to two adjacent ferroelectric capacitors is formed above the gate 104, the diffusion layer 101 and the gate 105. One ferroelectric capacitor including a ferroelectric film 112 and an upper electrode 113 and another ferroelectric capacitor including a ferroelectric film 114 and an upper electrode 115 are formed on the lower electrode 111. The ferroelectric capacitor including the ferroelectric film 112 and the upper electrode 113 is positioned above the gate 104. On the other hand, the ferroelectric capacitor including the ferroelectric film 114 and the upper electrode 115 is positioned above the gate 105.
Similarly, a lower electrode 117 common to two adjacent ferroelectric capacitors is formed above the gate 106, the diffusion layer 103 and the gate 107. One ferroelectric capacitor including a ferroelectric film 118 and an upper electrode 119 and another ferroelectric capacitor including a ferroelectric film 122 and an upper electrode 123 are formed on the lower electrode 117. The ferroelectric capacitor including the ferroelectric film 118 and the upper electrode 119 is positioned above the gate 106. On the other hand, the ferroelectric capacitor including the ferroelectric film 122 and the upper electrode 123 is positioned above the gate 107.
The upper electrode 115 and the upper electrode 119 are connected to the wiring 121 via plugs 116 and 120, respectively. Further, the wiring 121 is connected to the diffusion layer 102 through a plug 109.
As described above, in the conventional semiconductor memory device comprising ferroelectric capacitors, a ferroelectric capacitor comprising a ferroelectric film formed between a pair of the upper electrode and the lower electrode is formed on the memory cell transistor in a 1:1 relationship. Incidentally, in the semiconductor memory device comprising a ferroelectric capacitor, the similar structure is repeated in the left-right direction in FIG. 1, through the repeated structure is not shown in FIG. 1.
In the prior art shown in FIG. 1, a plurality of unit cells each comprising a single ferroelectric capacitor connected in parallel to a single memory cell transistor are connected in series. The particular construction is described in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-255483 as a ladder-type ferroelectric memory.
The conventional ladder-type ferroelectric memory disclosed in the literature quoted above attracts attentions in that a ferroelectric memory comprising a plurality of unit cells that are connected in series, each unit cell being constructed such that both ends of a capacitor (C) are connected between the source and drain of a memory cell transistor (T), said ferroelectric memory being hereinafter referred to as the xe2x80x9cseries connected TC-parallel unit ferroelectric memoryxe2x80x9d, is adapted for achieving a high degree of integration.
In the conventional ferroelectric capacitor, however, it is possible for the damage in the manufacturing process to produce a prominent influence with reduction in the capacitor size so as to deteriorate the capacitor characteristics. Particularly, in forming a capacitor by utilizing a reactive ion etching (RIE), it is necessary to ensure an alignment margin in view of the possibility of the over-etching of the side surface of the capacitor and in view of the deviation in the alignment of the mask. As a result, the shape of the capacitor obtained after the etching is rendered smaller than the design value, leading to the possibility that it is impossible to obtain a required capacitance.
It should also be noted that, since the ferroelectric film of the ferroelectric capacitor is formed of a single layer, the processing of the capacitor is rendered difficult and the capacitor tends to incur the damage on the process, if the size of the ferroelectric capacitor is reduced in accordance with reduction in the chip size of the semiconductor memory device. As a result, a problem is generated that the electrical characteristics, the reliability and the manufacturing yield of the semiconductor memory device are adversely affected. The present invention, which has been achieved in an attempt to overcome the above-noted problems, is intended to provide a semiconductor memory device that permits enhancing the degree of integration without decreasing the capacitance of the memory cell capacitor and to provide a method of manufacturing the particular semiconductor memory device.
According to an aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film.
According to another aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate, a first transistor formed on the semiconductor substrate and having a gate, a source formed of a first diffusion layer and a drain formed of a second diffusion layer, the first and second diffusion layers being arranged to face each other with the gate interposed therebetween, a second transistor formed on the semiconductor substrate, positioned adjacent to the first transistor, and having a gate, a source formed of a third diffusion layer and a drain formed of a fourth diffusion layer, the third and fourth diffusion layers being arranged to face each other with the gate interposed therebetween, a first plug electrode connected to the first diffusion layer, a second plug electrode connected to the second diffusion layer, a third plug electrode connected to the third diffusion layer, a fourth plug electrode connected to the fourth diffusion layer, a first bit line connected to the second plug electrode, a second bit line connected to the fourth plug electrode, a first electrode connected to the first diffusion layer through the first plug electrode, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, a third electrode formed on the second ferroelectric film, and a wiring connected to each of the third electrode and the third diffusion layer.
According to another aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate; a first transistor formed on the semiconductor substrate and having a gate, a source formed of a first diffusion layer, and a drain formed of a second diffusion layer, the first and second diffusion layers being arranged to face each other with the gate interposed therebetween; a second transistor formed on the semiconductor substrate, positioned adjacent to the first transistor, and having a gate, and a drain formed of a third diffusion layer arranged to face the first diffusion layer with the gate interposed therebetween, the first and second transistors sharing the source formed of the first diffusion layer; a first plug electrode connected to the first diffusion layer; a second plug electrode connected to the second diffusion layer; a third plug electrode positioned apart from the first plug electrode and connected to the first diffusion layer; a bit line connected to the second plug electrode; a first electrode connected to the first diffusion layer through the first plug electrode; a first ferroelectric film formed on the first electrode; a second electrode formed on the first ferroelectric film; a second ferroelectric film formed on the second electrode; a third electrode formed on the second ferroelectric film; and a wiring connected to each of the third electrode and the first diffusion layer through the third plug electrode.
According to another aspect of the present invention, there is provided a semiconductor memory device, comprising a semiconductor substrate; a transistor formed on the semiconductor substrate and having a gate, a source formed of a first diffusion layer and a drain formed of a second diffusion layer, the first and second diffusion layers being arranged to face each other with the gate interposed therebetween; a first plug electrode connected to the first diffusion layer; a second plug electrode connected to the second diffusion layer; a third plug electrode positioned apart from the first plug electrode and connected to the first diffusion layer; a bit line connected to the second plug electrode; a first electrode connected to the first diffusion layer through the first plug electrode; a first ferroelectric film formed on the first electrode; a second electrode formed on the first ferroelectric film; a second ferroelectric film formed on the second electrode; a third electrode formed on the second ferroelectric film; and a wiring connected to the third electrode and to the first diffusion layer through the third plug electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising forming a first diffusion layer on a semiconductor substrate and a second diffusion layer on the semiconductor substrate at a position a predetermined distance apart from the first diffusion layer; forming a first insulating film on the semiconductor substrate; forming a first plug electrode connected to the first diffusion layer in the first insulating film; forming a second plug electrode connected to the second diffusion layer in the first insulating film; forming a first electrode layer connected to the first diffusion layer through the first plug electrode above the semiconductor substrate; forming a first electrode by processing the first electrode layer in a predetermined shape; forming a first ferroelectric film on the first electrode; forming a second electrode layer on the first ferroelectric film; forming a second ferroelectric film on the second electrode layer; forming a third electrode layer on the second ferroelectric film; processing the second ferroelectric film and the third electrode layer in a predetermined shape; processing the second electrode layer in a predetermined shape; forming a second insulating film on the first ferroelectric film; forming a third plug electrode connected to the third electrode in the second insulating film; forming a fourth plug electrode connected to the second plug electrode in the second insulating film; and forming a wiring connected to each of the third plug electrode and the fourth plug electrode on the second insulating film.
Further, according to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising forming on a semiconductor substrate a first diffusion layer, a second diffusion layer a predetermined distance apart from the first diffusion layer, and a third diffusion layer a predetermined distance apart from the second diffusion layer; forming a first insulating film on the semiconductor substrate; forming a first plug electrode connected to the first diffusion layer in the first insulating film; forming a second plug electrode connected to the second diffusion layer in the first insulating film; forming a third plug electrode connected to the third diffusion layer in the first insulating film; forming a first electrode layer connected to the first diffusion layer through the first plug electrode above the semiconductor substrate; forming a first electrode by processing the first electrode layer in a predetermined shape; forming a first ferroelectric film on the first electrode; forming a second electrode layer on the first ferroelectric film; forming a second ferroelectric film on the second electrode layer; forming a third electrode layer on the second ferroelectric film; processing the third ferroelectric film and the third electrode layer in a predetermined shape; processing the second electrode layer in a predetermined shape; forming a second insulating film on the first ferroelectric film; forming a fourth plug electrode connected to the third electrode in the second insulating film; forming a fifth plug electrode connected to each of the second plug electrode and the second electrode in the second insulating film; forming a sixth plug electrode connected to the third plug electrode in the second insulating film; and forming a wiring connected to each of the sixth plug electrode and the fourth plug electrode on the second insulating film.